The ARM v3 MMU control module

Introduction - - This module provides MMU (Memory Management Unit) control for v3 architecture ARM processors (lives in Core/ARM/3). The v3 ARM MMU is a fairly versatile if simple MMU, with the ability to map memory in 1Mb, 64k and 4k granularities. Access to these pages may be restricted wholly or partly from user mode code.

Callability

Assembler:	`INCLUDE "ARMMMUH.s"`
C:	`#include "ARMMMU.h"`

HALError

Module name: "ARMMMU", 0, 0 (0x4d4d5241, 0x0000554d)

Codes:

(0x00):

Reserved

Portability API not portable
Code not portable

Constituents Entirely written in ARM assembler for speed

Porting notes None

Other Notes You must be in a supervisor mode to call any part of the module.

General use

All calls to and from the ARM v3 MMU control module are prefixed by ARMMMU_. The module uses only zero page memory and hence may be called at times when main memory is not functional.

To initialise and finalise the operation of this module, the usual calls ARMMMU_Initialise and ARMMMU_Finalise are provided. The general purpose call ARMMMU_Set is used to set the operation of the MMU. The calls ARMMMU_SetTranslationTableBase, ARMMMU_BeginL1PageTableBuild and ARMMMU_MakeL1PageTableEntries are used to build and use ARM MMU page mapping tables.

Typically, one would initialise the ARMMU module, then build L1 page tables and once built, they would installed using ARMMU_SetTranslationTableBase and then the MMU enabled using ARMMMU_Set.

ARMMMU_Initialise

Purpose	-	-	Initialises the ARM v3 MMU control module for subsequent use

Entry			None

Exit			R0 = Null if no error occurred, pointer to HALError otherwise

Interrupts			IRQ is disabled FIQ is unchanged

Processor Mode			Unchanged (see Notes)

Staticity			Alters zero page memory only

Use			None

Notes			You must be in a supervisor mode when calling this

ARMMMU_Finalise

Purpose				Deinitialises the ARM v3 MMU control module

Entry				None

Exit				R0 = Null if no error occurred, pointer to HALError otherwise

Interrupts				IRQ is disabled FIQ is unchanged

Processor Mode				Unchanged (see Notes)

Staticity				Alters zero page memory only

Use				None

Notes				You must be in a supervisor mode when calling this

ARMMMU_Set

Purpose				Sets the future operation of the MMU

Entry				R0 = bits to set R1 = bits to clear

Exit				R0 = Null if no error occurred, pointer to HALError otherwise

Interrupts				IRQ is disabled FIQ is unchanged

Processor Mode				Unchanged (see Notes)

Staticity				Alters zero page memory only

Use				This call offers the lowest level control of the operation of the MMU. There are three bits you may specify in R0 or R1, that being: bit 0: enable the MMU (ARMMMU_SETMMU) bit 1: enable address faulting (ARMMMU_SETADDRFAULT) bit 3: enable write buffering (ARMMMU_SETWB) bit 8: set system protection bit (ARMMMU_SETSYSTEM) bit 9: set ROM protection bit (ARMMMU_SETROM) Setting bits takes precedence over clearing bits. Please refer to the ARM ARM (the ARM Architecture Reference Manual) for more information about these bits.

Notes				You must be in a supervisor mode when calling this

ARMMMU_SetTranslationTableBase

Purpose				Sets the ARM MMU Translation Table Base register

Entry				R0 = desired MMU translation table base

Exit				R0 = Null if no error occurred, pointer to HALError otherwise

Interrupts				IRQ is disabled FIQ is unchanged

Processor Mode				Unchanged (see Notes)

Staticity				Alters zero page memory only

Use				None

Notes				You must be in a supervisor mode when calling this

ARMMMU_BeginL1PageTableBuild

Purpose				Initialises an L1 page table for subsequent use

Entry				R0 = address of new L1 page tables

Exit				R0 = Null if no error occurred, pointer to HALError otherwise

Interrupts				IRQ is unchanged FIQ is unchanged

Processor Mode				Unchanged

Staticity				Alters memory at R0 only

Use				An ARM v3 L1 page table occupies exactly 16k of memory - one 32 bit word entry for each Mb in the address range of the ARM (4Gb). This call prepares the 16k area of memory for subsequent use by other ARMMMU calls, including ARMMMU_SetTranslationTableBase

Notes				None

ARMMMU_MakeL1PageTableEntries

Purpose				Initialises an L1 page table for subsequent use

Entry				R0 = address of L1 page tables R1 = start section index R2 = start desired virtual address R3 = end desired virtual address R4 = desired domain, access permissions, caching and buffering status of the sections

Exit				R0 = Null if no error occurred, pointer to HALError otherwise

Interrupts				IRQ is unchanged FIQ is unchanged

Processor Mode				Unchanged

Staticity				Alters memory at R0 only

Use				This call fills the section entries starting at R1 with L1 page table entries mapping virtual address' R2 to R3 to that physical section. Each section entry is based on the contents of R4. This call allows quick and convenient setup of mapping of a range of virtual memory addresses to a physical set. Typical roles for this include the unification of a segmented physical memory arrangement and the remapping of memory in a multitasking system. Please refer to the ARM ARM (the ARM Architecture Reference Manual) for more information about using the ARM MMU and building page tables.

Notes				None